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Article by Ayman Alheraki in October 30 2024 01:16 PM

Understanding ARM 64-Bit Assembly Language A Comprehensive Guide to Instructions and Machine Code

Understanding ARM 64-Bit Assembly Language: A Comprehensive Guide to Instructions and Machine Code


 

Guide to common ARM 64-bit assembly commands in GNU Assembler (GAS) syntax, focusing on command categories like data movement, arithmetic, logical, and branching commands.

1. Data Movement Commands

CommandDescriptionExample
movMoves an immediate or register value to a register.mov x0, #5
ldrLoads a value from memory into a register.ldr x0, [x1]
strStores a value from a register into memory.str x0, [x1]
ldpLoads a pair of registers from memory.ldp x0, x1, [sp]
stpStores a pair of registers to memory.stp x0, x1, [sp, #-16]!
adrLoads a label address (relative) into a register.adr x0, label

2. Arithmetic Commands

CommandDescriptionExample
addAdds two registers or a register and an immediate.add x0, x1, #10
subSubtracts two registers or a register and an immediate.sub x0, x1, #5
mulMultiplies two registers.mul x0, x1, x2
udivUnsigned division of two registers.udiv x0, x1, x2
negNegates a register.neg x0, x1

3. Logical Commands

CommandDescriptionExample
andBitwise AND between two registers.and x0, x1, x2
orrBitwise OR between two registers.orr x0, x1, x2
eorBitwise XOR between two registers.eor x0, x1, x2
lslLogical shift left.lsl x0, x1, #2
lsrLogical shift right.lsr x0, x1, #2
notBitwise NOT.mvn x0, x1 (ARM equivalent)

4. Comparison and Test Commands

CommandDescriptionExample
cmpCompares two registers, updating flags.cmp x0, x1
cmnAdds two registers and updates flags.cmn x0, x1
tstPerforms bitwise AND and updates flags.tst x0, x1

5. Branching Commands

CommandDescriptionExample
bUnconditional branch to a label.b label
blBranch with link (for function calls).bl func
retReturns from a function.ret
cbzBranch if register is zero.cbz x0, label
cbnzBranch if register is not zero.cbnz x0, label
b.eqBranch if equal (zero flag set).b.eq label
b.neBranch if not equal (zero flag clear).b.ne label

6. Load and Store Commands with Pre- and Post-Increment

CommandDescriptionExample
ldrLoad register from memory with offset.ldr x0, [x1, #8]
strStore register to memory with offset.str x0, [x1, #8]
ldrbLoad byte from memory.ldrb w0, [x1]
strbStore byte to memory.strb w0, [x1]
ldrswLoad signed word (32-bit) and sign-extend to 64-bit.ldrsw x0, [x1, #4]
stpStore pair of registers to memory.stp x0, x1, [sp, #-16]!

Examples

Example 1: Simple Addition and Branch

Example 2: Function Call and Return

Example 3: Loading and Storing with Offset

Each of these commands is essential in ARM64 assembly, providing fundamental control over data manipulation, memory access, and program flow. Let me know if you’d like more in-depth examples for specific commands or applications!

 

Complete ARM 64-bit Assembly Instructions with Hexadecimal Encoding

InstructionAssembly SyntaxMachine Code (Hex)Description
MOVMOV x0, x1E1 00 00 00Move the value from x1 to x0
MOV ImmediateMOV x0, #5D2 80 00 05Move immediate value 5 into x0
ADDADD x0, x1, x20B 00 00 00Add x1 and x2, store result in x0
SUBSUB x0, x1, x24B 00 00 00Subtract x2 from x1, store in x0
ANDAND x0, x1, x20A 00 00 00Bitwise AND of x1 and x2, result in x0
ORRORR x0, x1, x22A 00 00 00Bitwise OR of x1 and x2, result in x0
EOREOR x0, x1, x22A 00 00 00Bitwise XOR of x1 and x2, result in x0
LDRLDR x0, [x1]B9 40 00 00Load word from address in x1 to x0
STRSTR x0, [x1]B9 00 00 00Store word from x0 to address in x1
BB labelVariesUnconditional branch to label
BLBL labelVariesBranch with link to label
CMPCMP x0, x12A 00 00 01Compare x0 and x1
TSTTST x0, x13A 00 00 00Test x0 against x1
CBZCBZ x0, labelVariesCompare x0 to zero, branch if zero
CBNZCBNZ x0, labelVariesCompare x0 to zero, branch if not zero
LDRBLDRB x0, [x1]B9 40 00 00Load byte from address in x1 to x0
STRBSTRB x0, [x1]B9 00 00 00Store byte from x0 to address in x1
LDURLDUR x0, [x1, #4]B9 40 00 00Load word from address in x1 with offset
STURSTUR x0, [x1, #4]B9 00 00 00Store word to address in x1 with offset
MULMUL x0, x1, x20B 00 00 00Multiply x1 and x2, store result in x0
SDIVSDIV x0, x1, x24B 00 00 00Signed divide x1 by x2, store result in x0
UDIVUDIV x0, x1, x24B 00 00 00Unsigned divide x1 by x2, store result in x0
LSRLSR x0, x1, #32A 00 00 00Logical shift right x1 by 3, result in x0
LSLLSL x0, x1, #32A 00 00 00Logical shift left x1 by 3, result in x0
RORROR x0, x1, #32A 00 00 00Rotate right x1 by 3, result in x0
RORROR x0, x1, #32A 00 00 00Rotate right x1 by 3, result in x0
BICBIC x0, x1, x20A 00 00 00Bit clear (AND NOT) of x1 with x2
POPPOP {x0, x1}A9 01 01 00Pop registers x0 and x1 from the stack
PUSHPUSH {x0, x1}A9 01 00 00Push registers x0 and x1 onto the stack
RETRETC0 03 5F D6Return from a function

Explanation of Key Instructions

  1. MOV: Move data from one register to another or load an immediate value.

  2. ADD/SUB: Basic arithmetic operations for addition and subtraction.

  3. AND/ORR/EOR: Bitwise operations for logical AND, OR, and XOR.

  4. LDR/STR: Load and store operations for transferring data between memory and registers.

  5. B/BL: Control flow operations for branching and function calls.

  6. CMP/TST: Comparison operations for setting condition flags.

  7. CBZ/CBNZ: Conditional branches based on the zero flag.

  8. MUL/SDIV/UDIV: Multiplication and division operations.

  9. LSR/LSL/ROR: Bitwise shifting operations for logical shifts and rotations.

  10. PUSH/POP: Stack operations for managing function calls and local variables.

Notes

  • Variability: The machine code for branch instructions (like B and BL) will depend on the address of the label they point to, so it will vary based on the code context.

  • Pseudo-instructions: Some assembly commands may be pseudo-instructions that are translated into one or more actual machine instructions by the assembler.

 

A table for ARM 64-bit (AArch64) architecture registers, along with a brief description of each register's typical role and example usage in Intel syntax-style ARM assembly.

RegisterNameDescriptionExample Usage
X0-X7Argument/ReturnUsed to pass the first 8 arguments to functions and to hold return values.mov x0, #10
X8Indirect ResultUsed to pass an additional return value or hold a pointer for indirect results.mov x8, x0
X9-X15TemporaryTemporary registers for general use within functions (caller-saved).add x9, x10, x11
X16, X17IP0, IP1Intra-procedure call temporary registers, used for procedure linkage.mov x16, #1
X18Platform RegisterReserved for platform-specific usage (varies by OS, e.g., in iOS/macOS it’s used as the "thread register").mov x18, xzr
X19-X28Callee-SavedPreserved across function calls (callee-saved), used to hold values that need to persist.mov x19, x0
X29Frame Pointer (FP)Points to the base of the current stack frame, often used to access local variables.stp x29, x30, [sp, #-16]!
X30Link Register (LR)Holds the return address for function calls.blr x30
X31 (XZR)Zero Register / Stack Pointer (SP)Reads as zero (XZR) when used as X31, or as the Stack Pointer (SP) in special instructions.mov x0, xzr

Additional Special Registers

RegisterNameDescriptionExample Usage
SPStack PointerPoints to the top of the stack, used for managing stack frames.stp x29, x30, [sp, #-16]!
PCProgram CounterHolds the current program address, generally not directly modified in AArch64.Implicit in branches
NZCVFlags RegisterHolds condition flags (Negative, Zero, Carry, Overflow) set by operations like comparisons.cmp x0, x1

Examples

1. Function Call Example

Passing arguments and returning values using X0-X7.

2. Stack and Frame Pointer Usage

Setting up and tearing down a stack frame.

3. Condition Flags Example

Using NZCV flags with conditional instructions.

These registers and examples showcase AArch64’s streamlined, efficient design, especially useful for high-performance applications, embedded systems, and modern operating systems.

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